Memories typically are implemented as bit cell arrays accessed via word line drivers, where the word line drivers are activated based on the decoding of row addresses associated with memory accesses. For data reliability and performance reasons, it often is advantageous to operate the bit cell array and the word line drivers at a higher voltage than the peripheral circuitry of the memory. This dual-voltage domain technique also is advantageous in that the peripheral circuitry of the memory can be placed in a low-power mode to reduce leakage current without disturbing the voltage supply to the bit cell array, thereby allowing the bit cell array to retain stored data.
The use of dual voltage domains typically requires the use of voltage level shifters between the peripheral circuitry and the word line drivers and bit cell array. Conventional level shifting implementations typically require a relatively large substrate area, thereby inhibiting their use in a memory topology having a relatively small memory cell pitch, particularly in memory cell topologies utilizing hierarchical word line decoding. These conventional level shifting implementations also typically implement relatively slow circuitry, which, being in the critical path between the peripheral circuitry and the word lines, impedes the performance of memory accesses. Accordingly, an improved technique for voltage level shifting in a multiple-voltage-domain memory would be advantageous.
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